Generally, it is possible to improve the performance of a transistor by biasing its substrate region. For example, biasing the substrate region of a transistor makes it possible to modulate the threshold voltage of the transistor.
As is well known, a substrate of the SOI type generally comprises a carrier substrate lying below a buried insulating layer (commonly referred to by the term buried oxide (BOX), itself lying below a semiconductor film, typically of silicon.
In certain cases, the silicon film may be fully depleted, in which case the substrate is referred to as being of the fully depleted silicon on insulator (FDSOI) type.
In other cases, the silicon film may be partially depleted, in which case the substrate is referred to as being of the partially depleted silicon on insulator (PDSOI) type.
Irrespective of the type of SOI substrate, the substrate region (or more simply “substrate” or “body”) of the transistor lies in the semiconductor film of the SOI substrate type.
In the case of a substrate of the PDSOI type, the substrate (body) of the transistor may be floating or may be electrically connected so that it can be biased.
In certain analog applications, it is particularly advantageous to have good control of the substrate (body) of the transistor.
There are solutions for biasing the substrate of a transistor formed on a substrate of the silicon on insulator type, particularly of the PDSOI type, such as forming a contact on a region of the semiconductor film which extends beyond the gate region of the transistor.
However, this type of solution has drawbacks. On the one hand, the contact is capable of generating parasitic effects, for example parasitic capacitances and resistances. On the other hand, the formation of a specific contacting zone for the substrate is not advantageous in terms of the surface occupancy and the design of the integrated circuit, particularly as regards the interconnections.
The formation of a contacting zone on a region of the semiconductor film which extends beyond the gate region hinders the formation of the gate contacting zones symmetrically on either side of the gate line. This type of arrangement, however, allows uniform biasing of the gate region.
A good compromise for controlling the potential of the substrate (body) of the transistor is to use a transistor whose source and substrate are connected. This is referred to as a “tied body”, which is used commonly by the person skilled in the art and avoids the drawback of a floating substrate.
In this tied body context, as illustrated in FIG. 1, one existing solution for reducing the number of contacting zones consists of a transistor T comprising a region R, which is in this case p-doped, formed in its source region RS, which is in this case n-doped, in contact with the substrate region, which is in this case p-doped.
Thus, biasing of the source region RS, conventionally by means of contact C formed thereon, also makes it possible to bias the substrate without having to form a specific contact.
However, this solution is not compatible with transistors of smaller dimensions, for example transistors produced in a 0.13 micrometer technology.
This is because the existing implantation technologies do not make it possible to form the p-doped region R in the source region RS without encroaching under the drain region RD. Moreover, this would risk greatly degrading the transistor during its operation.